Michael Morris (@M65C02A)

Michael has 30+ years of experience in aerospace/defense/commercial electronics. In his career Michael has worked in analog, video, RF, digital electronics and developed software/firmware for embedded processors in Fortran, Pascal, C/C++, Ada, and assembler. Michael has extensive experience with Xilinx FPGAs. As a hobby, Michael enjoys vintage computers and re-implementing classic microcomputers using HDLs and FPGAs.

Use DPLL to Lock Digital Oscillator to 1PPS Signal

Michael Morris July 24, 20168 comments

There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency oscillator on the leading edge of the 1PPS signal. In many cases, this will result in adequate performance. However, in situations where simple synchronization does not provide adequate performance, digital phase-lock techniques can be applied to a...

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