Michael Morris (@M65C02A)

Michael has 30+ years of experience in aerospace/defense/commercial electronics. In his career Michael has worked in analog, video, RF, digital electronics and developed software/firmware for embedded processors in Fortran, Pascal, C/C++, Ada, and assembler. Michael has extensive experience with Xilinx FPGAs. As a hobby, Michael enjoys vintage computers and re-implementing classic microcomputers using HDLs and FPGAs.

Use DPLL to Lock Digital Oscillator to 1PPS Signal

Michael Morris ● July 24, 2016●8 comments

Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.

No Threads Found